# Multiplying The Hard (And Fast) Way

A straightforward implementation of the sum-of-products in digital logic can be
described and specified in a way that is compact and readily understood.
Unfortunately, it is very difficult to make that implementation fast. Much recent work has
focused on computing a single product with minimal latency, as in the multiplier unit of a
general purpose microprocessor. I have been working on the related but distinct problem
of computing the sum of many products with maximum throughput. Both optimization
problems lead to circuit designs that are locally understandable but globally chaotic.
In this talk I will illustrate the problem using small examples and discuss the approach
I am taking to construct provably correct circuits when those circuits defy holistic reasoning.
To be presented Thursday, November 30th around noon.