**Steve Nuchia**

Multi-Dimensional Digital Signal Processing (DSP) applications commonly require calculation of sums of products having tens to hundreds of terms. This paper presents a novel digital logic structure for computing these sums.

The computational structure presented here is efficient in the sense that it uses less time and/or fewer logic gates compared to other methods. We assume a target implementation environment consisting of a large number of simple logic cells, such as that provided by commercial FPGA (Field Programmable Gate Array) chips.

The structure presented here is a pipeline with unstructured internal feedback. Because the feedback is unstructured it is impractical to apply our design technique by hand; a computer program is presented that generates pipeline configurations by heuristic search.

Other novel features of the design include combination of techniques to handle sign extension and rounding without waiting for carry propagation and a system-level technique for organizing 2-dimensional data samples in a memory array. These techniques make it possible to build a 15x15 FIR filter core for 10MHz 8-bit radar data using just two inexpensive off-the-shelf chips.

- Introduction
- Bit-Serial Multiplication
- System-Level Design
- Modeling Background
- Unstructured Feedback in a Summation Pipeline
- Design Generation and Proof of Correctness
- Conclusion
- About this document ...

Mon Dec 11 17:02:42 CST 2000