Given integers *x* and *y* such that *x*, *y*, and *x*+*y* are
representable as *n*-bit two's-complement numbers,

where and

The sum property means that hardware adders can be built without
regard to the interpretation -- signed or unsigned -- of the
bit vectors being added. This is true when the lengths of the
bit vector output is the same a both input bit vectors. When
the sum is not representable we say that *overflow* or
*underflow* has occurred.

Mon Dec 11 17:02:42 CST 2000