Sign extension gives us a mechanism for computing sums
without worrying about overflow or underflow. If
then and so the sum is representable as an *n*+1-bit
two's complement number. The *n*+1-bit sum of the extended input vectors
represents the sum of the input quantities. Since the sign extension
rule differs for signed and unsigned numbers the hardware must be specialized
to the interpretation.

If the inputs are known to represent unsigned quantities then the
``extension'' consists of zero bits which will not influence the
output of the addition circuit. In this case the bit *n* of the
output is the ``carry out'' bit of the adder.

Mon Dec 11 17:02:42 CST 2000