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Synchronous Logic

A flip-flop is a logic element with a special input known as a clock. In effect, the flip-flop samples its other inputs on each active edge (state transition) of the clock signal. The output of a flip-flop is, in general, a function of the input and the output(s) at the time of the clock edge.

A variety of named flip-flop configurations exist, distinguished by the function of the inputs and output they compute. All can be modeled as a combinational circuit combined with a "D" flip-flop or latch circuit element. A latch has a single input and a single output. The input signal is copied to the output on each clock edge.

A synchronous logic circuit is composed of combinational circuits with latched outputs. The latches share a common clock signal which serves to divide time into discrete intervals. Ignoring the ultimate inputs, signals change only on clock edges and, so long as each combinational circuit has delay less than the minimum clock period, it is possible to ignore timing details.

The latches also give synchronous circuits memory: the output may in general depend on the history of input values rather than on just their instantaneous values. The memory property also makes it possible to continue ``working on'' a set of input information after the input signals have changed. This is the foundation of logic pipelining.



Stephen W. Nuchia
Mon Dec 11 17:02:42 CST 2000