In a digital signal filtering application there is an underlying sequence of data values and successive input vectors are overlapping subranges

One customarily chooses
a reset state for the internal latches equivalent to assuming
for all *i*<0. While *m*=1 in many applications, *decimation filters*
are an important exception. There the *stride*, *m*,
is the decimation factor.

After has been input, all but the last *m* of the
values in have been communicated to the circuit. In this circumstance
we require only *m* wires to supply the circuit with the new inputs. When
*m*=1 the data stream is said to be *serial*; this is frequently
the case in audio applications.

The *n*-*m* overlapping data values must be retained inside the sum-of-products
circuit from one problem to the next. The shift register arrangement that
accomplishes this is the well known *tapped delay line*.

Mon Dec 11 17:02:42 CST 2000